Most current network devices are based on a storage-forwarding mechanism, i.e. a data packet is firstly stored in a network device after entering into the network device and then being read out and forwarded after the network device performs an operation, e.g. finding a next-hop.
Generally, a data packet to be forwarded may be accessed in the network device for many times. Thus, the efficiency of the network device for accessing the data packet greatly affects data packet transmission efficiency. For example, the data packet is firstly stored in an ingress linecard waiting for routing forwarding search, then is read out and transmitted to an egress linecard through a backplane switched network and is stored in the egress linecard waiting for a QoS scheduling. A data packet meeting QoS requirements will be read out and transmitted. Therefore, in order to improve the data packet transmission efficiency, the network device needs to meet the following demands when the data packet is accessed.
1) The storage capacity of the network device for storing data packets should be larger than or equal to RTT×R bits, wherein RTT (Round Trip Time) denotes a line round trip time on the linecard, and R denotes a line rate on the linecard. Suppose RTT is 200 ms, a network device with a 10 Gbit interface needs to have a storage capacity of 10 Gbit/s×0.2 s, i.e. a storage capacity of 2 Gbit.
2) The network device needs to have high bandwidth for accessing data packets. Suppose a network device with a 10 Gbit interface needs to access each data packet twice, the network device needs to have an access capacity of 20 Gbit bandwidth.
In practical applications, a data packet processing chip in the network device is usually an Application Specific Integrated Circuit (ASIC) chip or a Field Programmable Gate Array (FPGA) chip, whose storage capacity cannot meet the storage requirements of data packets. In order to meet the storage requirements, as shown in FIG. 1, a Random Access Memory (RAM) with high bandwidth and a large storage capacity is usually externally connected with the data packet processing chip of each linecard in the storage-forwarding based network device. Referring to FIG. 2, a control logic is configured in the data packet processing chip. It stores data packets received by the data packet processing chip into the RAM in turn according to a queue management mechanism of a First-In-First-Out (FIFO) storage, reads data packets out of the RAM in turn and transmits the data packets to the data packet processing chip.
Among most RAMs, Double Data Rate 2 (DDR2) Synchronous Dynamic Random Access Memory (SDRAM) and Double Data Rate 3 (DDR3) SDRAM are often selected for their larger capacity, higher rate and lower price.
However, even if the DDR2 SDRAM or the DDR3 SDRAM with larger capacity and higher rate are selected to store data packets, continuous reading/writing operations of the data packets may be restricted due to some features of the DDR2 SDRAM and the DDR3 SDRAM. For example, when accessing different rows in a same BANK of the DDR2 SDRAM, a delay between successive active (ACT) commands to two rows will result in a bus idle of the DDR2 SDRAM; when accessing any row in any BANK of the DDR2 SDRAM, e.g. a read operation or a Precharge operation on the row, may also result in the bus idle of the DDR2 SDRAM.
However, the existing control logic for accessing data packets does not consider how to avoid an effect of the above restriction on the data packet accessing efficiency. It performs a random reading/writing operation to the DDR2 SDRAM and the DDR3 SDRAM, and thus cannot meet the high bandwidth requirements for accessing the data packets.
Referring to FIG. 3, take the reading of data packets in a burst mode as an example. The control logic continuously reads data packets from different rows in the same BANK of an external DDR2 SDRAM.
At clock cycle T0, an ACT command is transmitted to the external DDR2 SDRAM to activate a row in the BANK of the external DDR2 SDRAM.
At clock cycle T1, an RD command is issued to the external DDR2 SDRAM, and the external DDR2 SDRAM starts a read operation to the row in the BANK.
At clock cycles T2˜T3, the external DDR2 SDRAM continues the read operation to the row in the BANK.
At clock cycle T4, wait for the external DDR2 SDRAM to perform a Precharge operation to close the row.
At clock cycles T5˜T6, the external DDR2 SDRAM outputs the read data packet through a bus.
At clock cycle T7, wait for a delay between successive ACT commands of two rows.
At clock cycle T8, an ACT command is issued to the external DDR2 SDRAM again to activate a next row in the BANK of the external DDR2 SDRAM.
At the 8 clock cycles from T0˜T7 in the above procedure, the bus of the DDR2 SDRAM is occupied only at 2 clock cycles from T5˜T6, the bus usage ratio during the continuous read operations is only 25%. It is similar for continuous write operations. Moreover, a switch between the read operation and the write operation will result in bus idle of different clock cycles due to the features of different DDR2 SDRAMs, i.e. the bus usage ratio is lower when the read operation and the write operation are performed alternately. In addition, after a row is activated at clock cycle T0, a read command may be issued to the row at clock cycle T1 after 0 clock cycle is delayed subject to a pre-configured parameter tRCD of the DDR2 SDRAM, and data packets are read out through the bus of the DDR2 SDRAM after 4 clock cycles are delayed subject to parameters AL and CL. In practical applications, after a row is activated at clock cycle T0, the read operation to the row may be performed after at least one clock cycle delay through configuring the parameter tRCD because the bus rate of the DDR2 SDRAM is high, or the delay of reading data from the bus may be further prolonged through configuring the parameters AL and CL. In this way, the bus usage ratio is further decreased. As to the write operation, the situation is similar.
As can be seen from the above, the existing storage-forwarding based network device can use the RAM to meet the storage requirements of data packets, but the control logic cannot meet the high bandwidth requirements for accessing data packets, thereby affecting the data packet accessing efficiency under the storage-forwarding mechanism.